Akeana 1000 Series
A Line of 64-bit RISC-V Ultra-High Performance Processors
Akeana 1000 Series Processors
The Akeana 1000 Series of processors are highly configurable and customizable, supporting applications from smart homes and wearables, to automotive ADAS applications.
The Akeana 1000 Series is optimized for a broad range of applications, offering both In-Order and Out-of-Order architectures to provide customers the range of cores and architectures needed for a range of computation requirements. Issue width ranges from single to Quad issue.
The Akeana 1000 Series is the mid range of the 3 series of Akeana processors, offering customers one of the broadest processor IP portfolios.
9-stage pipeline (In-Order) and 12-stage pipeline (Out-of-Order)
MMU with 256-entry, 4-way TLB
Advanced Security Features
39-bit Physical and Virtual Addressing
Akeana 1000 Series Processor Diagram
Akeana 1000 Series Standard Configurations
| Basic akeana 1000 Core Configuration | Product | Standard Features | Typical Applications |
|---|---|---|---|
| RV64GCB_Zicbo instruction set Full RVA22 RISC-V Profile Single- & double- precision floating-point User Mode Supervisor Mode 48 bits Virtual Address range 39 bits Physical Address range Scalable to fully coherent many core clusters ECC support AXI/ACE (512 bits) Physical memory Protection (PMP) with 16 entries MU | Akeana 1100 | 9-stage, in-order pipeline Dual instruction dispatch L1 I-cache: 16 KB/core L1 D-cache: 16 KB/core MMU with 256-entry, 4 way TLB | High-end microcontroller Download Product Brief |
| Akeana 1200 | 9-stage, in-order pipeline 3-way instruction dispatch Secondary ALU in pipeline L1 I-cache: 32 KB/core L1 D-cache: 32 KB/core MMU with 256-entry, 4-way TLB | Edge gateway Download Product Brief |
|
| Akeana 1300 | 12-stage, out-of-order pipeline 4-way instruction dispatch L1 I-cache: 32 KB/core L1 D-cache: 32 KB/core L2 cache: 256KB MMU with 512-entry, 4-way TLB | Edge gateway, "Little" core in Big/Little configurations |
Add On Options Include
- L1 Instruction cache, up to 128 KB
- L1 Data cache, up to 64 KB
- L2 cache, up to 1 MB
- Physical Address width up to 48bits
- Virtual Address width up to 48bits
- Shared, unified Last-Level Cache (LLC), up to 16 MB
- Scalar Cryptographic (K) extension
- Scalar Cryptographic (K) extension
- Hypervisor (H) extension
- Packed SIMD (P) extension*
- Vector (V) extension (64 to 512 bits)
- Physical Memory Protection (PMP) , 1 to 64 entries
- TLB up to 2048 entries, 8 ways
- Custom instructions