Akeana 5000 Series
A Line of 64-bit RISC-V Ultra High Performance Processors
Akeana 5000 Series Processors
The Akeana 5000 Series of processors are highly configurable and customizable, supporting applications such as mobile applications computation, Data Center and Cloud networking applications. The Akeana 5000 Series is optimized to give the industry leading edge performance, capable of Android OS application computation, with the ability to scale to 100’s of coherent processors.
The Akeana 5000 Series is the high range of the 3 series of Akeana processors, offering customers one of the broadest processor IP portfolios
12-stage pipeline (Out-of-Order), with up to 8-issue
MMU with 2048-entry, 8-way TLB
Multi-Threaded support (option)
Up to 48-bit Physical and Virtual Addressing
Akeana 5000 Series Processor Diagram
Akeana 5000 Series Standard Configurations
| Basic 5000 Series Configuration | Product | Standard Features | Typical Applications |
|---|---|---|---|
| RV64GCVBK_Zicbo + USH instruction set Full RVA23 RISC-V Profile Single & Double-Precision Floating-Point User Mode Supervisor Mode Hypervisor extension Vector extension (128 bits) Vector Crypto extension 12-stage, out-of-order pipeline 48 bits Virtual Address range 256K L2 cache Scalable to fully-coherent many-core clusters ECC support AXI/ACE (512 bits) Physical Memory Protection (PMP) with 16 entries MMU | Akeana 5100 | 4-way instruction dispatch L1 I-cache: 32 KB/core L1 D-cache: 32KB/core 33 bits Physical Address Space MMU with 512-entry, 4-way TLB | "Big" core in Big/Little configurations |
| Akeana 5200 | 6-way instruction dispatch L1 I-cache: 32 KB/core L1 D-cache: 32 KB/core L2 cache prefetcher 39 bits Physical Address Space MMU with 1024-entry, 4-way TLB | “Big” core in Big/Little configurations |
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| Akeana 5300 | 8-way instruction dispatch L1 I-cache: 64 KB/core L1 D-cache: 64 KB/core L2 cache prefetcher 39 bits Physical Address Space MMU with 2048-entry, 8-way TLB | Datacenter / Infrastructure compute core Download Product Brief |
Add On Options Include
- L1 Instruction cache, up to 128 KB
- L1 Data cache, up to 64 KB
- L2 cache, up to 1 MB
- Shared, unified L3 Cache, up to 16 MB
- Physical Memory Protection (PMP), 1 to 64 entries
- Virtual Address width up to 48 bits
- Physical Address width up to 48 bits
- Custom instructions
- Up to 2048-entry, 8-way TLB