Akeana is a venture funded RISC-V startup founded in early 2021 by leaders in our industry. Our semiconductor IP offerings include low end microcontroller cores, mid-range embedded cores, high end laptop/server cores along with coherent and non-coherent interconnects and accelerators.
Akeana was founded with the goal of bringing maximum performance and capabilities to the RISC-V ecosystem. The team is leveraging its vast experience, from working on successful projects like ThunderX and Vulcan, to bring you best-in-class CPU and System IP.
We are providing a complete suite of RISC-V Core IP – including microcontrollers, Big-Little application cores, high performance data center cores, and multi-threaded cores for networking and other high throughput applications. The highly configurable design methodology also allows Akeana to provide cores optimized for specific vertical markets and applications. In addition to cores, Akeana provides a complete suite of system IP including cluster caches, non-coherent interconnects (AXI), coherent interconnects (CHI), RISC-V interrupt controllers, RISC-V IOMMU, as well as security IP.
Rabin Sugumar was Distinguished Engineer and Chief Architect at Marvell/Cavium and built and led the architecture group for the ThunderX Arm server processor line. Most recently he led the architecture of the ThunderX3 processor, which had industry leading single thread performance and socket level performance at time of silicon. Prior to Marvell/Cavium, he was at Broadcom where he was one of the lead architects on the server processor that became ThunderX2. ThunderX2 was the first Arm server to achieve single thread and socket level performance comparable to high end Intel Xeon servers and paved the way for Arm servers in the data center. During Rabin’s career, he has also worked on architecture and design of vector processors at Cray Research, early multi-threaded and out-of-order SPARC processors at Sun Microsystems, and InfiniBand adapters at Sun Microsystems/Oracle. Rabin obtained his PhD in Computer Science and Engineering from the University of Michigan. The cache simulator he wrote during his PhD is still widely used in academia. Rabin has over 25 years of experience in CPU architecture and design, and 28 granted patents.
Nitin Rajmohan is a design verification leader and has a long track record of building large multi-site validation teams, validating complex cores, and producing high quality silicon. Most recently, Nitin was the Senior Director of Verification on the Arm server program at Marvell and led core validation on the ThunderX3 program. Prior to ThunderX3 Nitin led core validation on ThunderX2 at Broadcom and later Cavium and Marvell. Nitin also led the post-silicon validation effort on ThunderX2 and was part of the team that successfully delivered ThunderX2 for the Astra Supercomputer – the first Arm based system to feature in the Top500 Supercomputers. Nitin has also led core validation on MIPS based designs at Broadcom/Netlogic and worked on x86 validation at Intel.
Abbas Rashid has led design and development teams for several successful chips over the course of his career. Most recently Abbas was the Director of Logic design on the ThunderX Arm server program at Marvell, where he led design for the CPU Core, Memory Subsystem, and DFT. Before Marvell, Abbas was at Broadcom/Netlogic as head of the Core CPU Design team. The team delivered the industry’s highest performance embedded MIPS-based multi-core processor. Subsequently, after the product transitioned to Arm from MIPS, the core team lead by him delivered the industry’s highest performance Arm server processor and next generation multi-core solution. Abbas has over 25 years of experience in CPU design and over 25 granted patents.